Intelligent Clock Networking Solutions that Adapt on the Fly
The Maestro platform automates the development
of robust application-optimized clocking solutions.
These powerful new tools are used in many SoC applications for video signal processing, frequency synthesis, clock synchronization, demodulation, precision timing, or improved clock signal quality. Maestro solutions provide better operating characteristics than traditional analog implementations. They can operate at ultra-low nanowatt voltages or high performance multi-Ghz frequencies while requiring just a small footprint.
Maestro AI is an intelligent clock networking solution that can automatically compensate for on-chip variation and balance insertion delays. Solutions are dynamic, self-regulating, and automatically adapt to changing conditions during runtime. Generally, all clock networking solutions are static and do not adapt to change. But Maestro AI is dynamic and makes adjustments on the fly. It automatically balances clocking at hierarchical blocks by inserting delays to reduce inter-block uncertainty. This ensures clocking is always synchronized and eliminates wasteful system overdesign.
The Maestro platform combines a clock architecture, software automation, and application-optimized IP to solve common clocking challenges. Maestro AI incorporates TrueDigital™ modules including Clock Generator Modules (CGM), Smart Clock Modules (SCM), and Phase Shift Modules (PSM). CGMs generate an output signal with a phase that is related to an input or reference signal. SoC applications incorporate CGMs for a variety of functions including clock synchronization and improved signal quality along the clock path. SCMs automatically sense and compensate for on-chip variation and skew in the SoC clock path during runtime. They eliminate the need for global clock tree balancing due to differing block sizes. PSMs advance or delay the clock and are used to eliminate clock skew. They have a tunable delay interval that can be adjusted on the fly.
Included in Maestro AI is a master RTL codebase that can be configured to generate code that precisely meets application specifications. Maesto AI’s fully synthesizable architectures enable rapid RTL-to-GDS implementation and optimization. The platform is designed to work seamlessly with existing digital tools and methodologies to speed up development. Maestro AI intelligent clock distribution networks are used in high-performance solutions across AI, aerospace, networking, and other high-performance computing markets. Silicon-proven across foundries including TSMC, GF, UMC, and Fujitsu, 'Maestro AI solutions are commonly used by customers in volume production.
Product Line Highlights
- Automatically balances global clock tree by compensating for differing block sizes
- Equalizes the source latency for all blocks across the SoC
- Senses and compensates for on-chip variation and skew in the clock path
- Eliminates the need for countless buffers for inter-block data transfer
- Ultra low voltage operation with no headroom limitation
- Extreme environment operation for extended temperatures and radiation hardness