Aeonic Connect - Clock Network

Taming Your Clock Network

Movellus Aeonic Connect™ - an Intelligent Clock Network™ that actively compensates for static and dynamic silicon variation

Traditionally all clocks on a chip start at a singular point, and clock architects use a variety of structures, including CTS, H-Tree and meshes, along with sophisticated techniques including staging flops, buffers, cloned gates, etc. to deliver a clock that meets the design’s performance requirements to each flop across the chip.

Clock architects have refined these techniques over the years, but they translate into tradeoffs in performance, power and area (PPA), and something that isn’t fully appreciated - TIME.  As SoCs get more complicated, not only do the PPA tradeoffs become more challenging, but the implementation effort takes more and more time as a portion of the overall design cycle. 

Aeonic Connect™ is an Intelligent Clock Network™ that fundamentally reimagines how clock topologies are implemented by automatically compensating for divergent clock paths through a novel closed-loop architecture. The Aeonic Connect platform continuously ensures that each flip-flop in a Aeonic domain remains synchronized with the clock source through this closed loop system.

The clock is the heartbeat of silicon design, and one of the most complex networks in an SoC, influencing every aspect of the system from timing closure to peak power demand, and from chip architecture to layout. Designs of all sizes and technology nodes experience SoC-level clock distribution challenges that lead to compromises in tapeout schedules and power challenges.

The Aeonic platform introduces the concept of an Intelligent Clock Network™ that dynamically compensates for on-chip variations (OCV) and propagation delays, lowers power consumption and simplifies timing closure. The platform is in use by an array of applications ranging from ultra-low power edge AI devices to performance-centric cloud datacenter compute and AI offerings.

Product Line Highlights
Faster Timing Closure Reduces both the number and magnitude of violating paths
Dynamic Compensation Mitigates static and dynamic silicon variation effects
Smaller Area Saves area as fewer buffers, and smaller clock drivers are needed
Optimized Power Efficiency Delivers the performance of a mesh at the power of a tree
Process Node Independent Supports processes from all foundries
Leverages Existing Tools Uses existing digital tools and methodologies