Transparency, empowerment, and opportunities are what we promote. Join us as we disrupt how analog design is done.

We are a fast-paced company. We challenge our team members to exceed their own expectations and to collaborate with others and bring products to market that exceed our customer’s expectations.

Benefits:  We provide competitive benefits including Medical, Dental, Vision & more.

Current Openings

Who You’ll Work With

Our creative and talented team at Movellus is disrupting the way SoCs are designed. You will work with front-end teams to understand chip architecture and drive physical aspects early in the design cycle, driving them to refine their design for physical design closure. You will be the lead to drive the backend process through the entire implementation flow including floor planning, Placement, CDC checks, static timing verification and equivalence checks, with special focus on power and die size optimization.

Moreover, you will drive the development of Movellus’ disruptive new SoC design methodology.

What You Will Do

  • Responsible for floor planning, physical synthesis and physical design closure of complex designs at 1GHz+ clock cycles
  • Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.
  • As a member of the physical/implementation design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists and drive execution.
  • Work with Frontend team to understand the RTL design and drive physical aspects early in the design cycle for physical design closure.
  • Resolve design and flow issues related to physical design, identify potential solutions

Who You Are

  • You are a HW engineer with 5+ years of related work experience with a broad mix of technologies including
  • Excellent understanding of ASIC design methodologies from netlist to GDS
  • Familiar with all aspects of physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning.
  • Familiar with hierarchical design approach, top-down design, budgeting, timing constraints and physical convergence.
  • Hands on experience in block level implementation including physical synthesis, placement, routing and optimization with Innovus/ICC2 and timing closure including OCV
  • Familiarity with low power design and custom placement implementation
  • Experience with large designs utilizing state of the art sub 16/14 nm (FinFET) technologies
  • Strong communication skills and ability to work as a team player
  • You should also have hands on experience with the following Tool sets
    • Floor planning and P&R tools
    • Synthesis Tools Synopsys DC/DCG; Cadence Genus
    • Static Timing / Signoff Timing verification (Primetime/Tempus).
    • Physical Design Verification DRC/LVS
  • Scripting TCL is required; Python is a plus

Bachelor’s or Master’s Degree in Electrical or Computer Engineering required

About Movellus

Movellus is disrupting the SoC design paradigm by leveraging its patented VirtualAnalog technology. With over a decade of R&D, this technology is being leveraged by our customers in applications ranging from IoT to artificial intelligence.

Come join the movement that is shifting the landscape of chip design.

We’re looking for a talented intermediate to senior level ASIC engineer to join our passionate, mission-driven, tightly-knit Toronto team. As part of the development team, you will play a critical role developing disruptive industry leading technology. You will have a variety of responsibilities and be able to apply your skills and knowledge to design and deliver key new technology that forms the backbone of Movellus IP. The Movellus team will be committed to your intellectual, technical, and professional development.

Our office is inside the Spaces hub at the Toronto Queen West location surrounded by startups and amazing people in an open and fun environment. Plenty of snacks, tea and coffee, and a great outdoor patio to enjoy on your down time.

Core Responsibilities

  • Functional verification of RTL-level IP and systems
  • Working directly with application engineering to support customer engagements
  • Test coverage analysis
  • Working with silicon validation team for post-silicon analysis
  • Sign-off ownership for IP functionality
  • Prioritizing tasks and achieving milestones
  • Project planning

Desired Experience

  • Block-level and system-level Verilog verification in an ASIC environment
  • Familiarity with Verilog, UVM, System Verilog and Python
  • TCL is a plus
  • Full-flow verification (RTL, gates, gates with SDF)
  • ASIC tapeout experience
  • Familiar with coverage metrics including functional coverage
  • Use of industry standard simulation tools
  • Development of ASIC regression suites
  • Full-system performance testing
  • Use of version control systems
  • Working in a multi-person development team sharing the same codebase, comfortable with industry standard software version control systems
  • Strong communication skills and ability to work as a team player

Bonus Experience

  • RTL design
  • Design for test (DFT)
  • Working in a fast-paced startup environment
  • Working directly in customer engagements

A Bachelor’s degree in Electrical Engineering is required. MSEE preferred.

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