All-Digital Solution Addresses
SoC Clocking Challenges
Movellus Maestro™ clock distribution network platform delivers chip-level architectural
innovations to improve SoC performance while reducing power consumption.
Maestro solves SoC-level clock distribution challenges in high performance and ultra low power chips. This includes on-chip variation, jitter, clock skews, setup and hold violations, peak current, and switching noise. All of these clocking challenges continue to increase with process node scaling. The Maestro platform provides application-optimized digital components that intelligently orchestrate timing across an SoC.
The platform uses Movellus TrueDigital™ components which are all-digital, fully synthesizable PLLs (phase-locked loops), DLLs (delay-locked loops), Smart Clock Modules, and Virtual Mesh. These components achieve unrivaled power savings and offer superior PPA to traditional analog and partial-digital solutions. TrueDigital technology offers nanowatt power consumption, a wide voltage range, up to 10X smaller area, and low jitter.
The Maestro clocking solution with TrueDigital offers up to 30% dynamic power reduction, 15x peak power savings, 30% performance gains, and 5x faster timing signoff.
Optimizing SoC Applications
Modern applications have complex clocking requirements. Maestro provides critical clocking capabilities that are optimized for specific SoC
applications. It dramatically improve the entire chip’s power, performance, and area in a wide variety of markets.
Product Line Highlights
Maestro is our flagship clock distribution network platform that intelligently orchestrates precision clocking in high performance and ultra low power SoCs. Three versions of the product are available, each addressing specific requirements based on the complexity of the application.
We also offer our all-digital fully synthesizable TrueDigital PLLs and DLLs. These two products are available for select applications that require a simple drop-in replacement for analog PLL/DLL functionality.