Analog Gone Digital
8X Smaller | DFT | Days vs. Months | Lower Power
We believe analog should not be a bottleneck in SOC designs, which is why we automatically create functions such as PLLs and DLLs in a fraction of the time compared to traditional analog implementations, with the same or better performance.
From Edge to Cloud Computing
Movellus’ silicon proven, easily customizable PLLs and DLLs elegantly exploit the continuum of performance vs. area and power. Ranging from ultra-low power designs running at less than 10kHz for edge AI applications to beyond 10GHz with sub-picosecond jitter for multi-core processors.
Optimized Solutions in Days vs. Months
Rather than architecting your SOC around available components, which most likely are not optimized for your design, let us optimize one to meet your exact specifications.
Process Portability & More
- Process portability: rapidly move your design from one foundry to another
- Minimal layers: only 8 layers of metal or less, allowing routing over the IP. This eliminates power distribution disruption caused by analog solutions
- Reliability: reliability checks such as EM/IR and aging flows are much more mature and predictable
- Coverage: full digital DFT capabilities allow unparalleled ATE fault coverage
What Movellus Customers are Saying
“We’re working on a very different way of meeting the needs for neuro-network inference at the edge.
“The primary feature we felt was important at the end of our evaluation, was the ability for Movellus to react to ongoing process and PDK changes, and give us an optimized PLL for what became our final process definition. That was something that we didn’t see was going to be possible from a vendor who was just offering a piece of IP from their library, or from a vendor who is really working from an analog background, where adapting to those process changes would take them quite a bit of time and effort.
“When it came to performance and power, we’re very pleased with the result, and we think it’s better than we could have gotten from analog.”
VP of engineering