
- Mo Faisal CEO and Founder


- Intel Innovation 2022



Movellus Aeonic™ Digital IP Platform
Architectural Solutions for Complex SoCs
Movellus Aeonic™ IP delivers chip-level architectural
innovations to improve system performance through feature-rich, synthesizable IP.
Movellus Aeonic is an IP platform that solves system-level issues through first principles. The foundation of the Aeonic platform is Movellus’ core expertise in converting traditionally analog functions into the digital domain and combining this with system-level knowledge to solve challenging SoC problems in innovative ways with process portable solutions.
Movellus Aeonic is a configurable platform that helps architects address challenges faced in advanced silicon designs, such as droop response, fine-grain performance tuning, and latency.
- “We knew that we that had to design neural processors with not only exceptional performance, but with chips that achieve that performance at very low power and in a very small die area. Therefore, choosing the right IP partner critical for us. We put our trust in Movellus because their clock generation and CGM solutions fit our low-power architecture perfectly. They proved to be the right choice. In addition, to the architectural fit, their support from their application team helped us meet the very tight timelines we had set for introducing our solution to the market. That is the reason we continue to work with Movellus and as we work to expand our award-winning portfolio of neural decision processor for edge AI.”
David Garrett
Chief Architect and SVP Engineering
- Movellus’ clocking solution had the smallest area for the frequency and process combination – no other vendor came close.
Dr. Nathan Roberts
VP of Engineering at Everactive Technologies
- "With a chip that has over 1000 RISC-V processors that are running at extremely low power levels, clocking was one of the more important design considerations for this project. We work directly with the Movellus engineering team to design and debug this innovate clock distribution network. Their CGM and AWM solutions really helped us to achieve our aggressive performance targets while keeping the power within our budget."
Darren Jones
Vice President VLSI Engineering