
- Mo Faisal CEO and Founder


- Intel Innovation 2022



Reduce Power. Improve Time to Market. Lower Costs.
Movellus Aeonic™ Intelligent Clock Networks™ deliver chip-level architectural
innovations to improve SoC performance while reducing power consumption.
In the past 25 years clock topologies have remained largely static. Aeonic, is an Intelligent Clock Network IP platform that modernizes clock implementation to keep pace with advanced SoCs. The platform actively compensates for static and dynamic silicon effects driving a substantial reduction in power and clocking complexity with seamless integration into current design flows.
Aeonic™ helps architects solve chip-level clock network challenges in high-performance SoCs that include timing complications due to static and dynamic effects. The Aeonic platform provides a flexible, efficient, and application-optimized solution that intelligently orchestrates timing across a SoC, helping semiconductor providers meet their power and time-to-market goals.
- “We knew that we that had to design neural processors with not only exceptional performance, but with chips that achieve that performance at very low power and in a very small die area. Therefore, choosing the right IP partner critical for us. We put our trust in Movellus because their clock generation and CGM solutions fit our low-power architecture perfectly. They proved to be the right choice. In addition, to the architectural fit, their support from their application team helped us meet the very tight timelines we had set for introducing our solution to the market. That is the reason we continue to work with Movellus and as we work to expand our award-winning portfolio of neural decision processor for edge AI.”
David Garrett
Chief Architect and SVP Engineering
- Movellus’ clocking solution had the smallest area for the frequency and process combination – no other vendor came close.
Dr. Nathan Roberts
VP of Engineering at Everactive Technologies
- "With a chip that has over 1000 RISC-V processors that are running at extremely low power levels, clocking was one of the more important design considerations for this project. We work directly with the Movellus engineering team to design and debug this innovate clock distribution network. Their CGM and AWM solutions really helped us to achieve our aggressive performance targets while keeping the power within our budget."
Darren Jones
Vice President VLSI Engineering