Performance Tuned SoCs Are Essential to Cost Effective and Scalable AI
Enabling Edge and Datacenter AI Silicon to Handle Dynamic Customer Workloads
AI and ML workloads are growing in popularity across many industries, leading to great variability in operation types and composition. In February 2021, Microsoft announced its 17 billion parameter language model T-NLG. Less than one year later, Google shattered that record with its 1.6 trillion parameter model Switch-C, almost a 100x increase in model size.
Models (language and vision) continue to grow in size and complexity at an exponential rate. The uncertainty and rapid model growth is driving AI silicon designers to increase performance at unprecedented rates, which has power and time-to-market implications.
While specialized in handling a narrow set of computational operations, AI/ML chips face similar power challenges as CPUs and GPUs. Varying customer workloads create unpredictable voltage droops that can induce timing glitches. As designers build larger synchronous regions, simultaneous switching noise creates larger ripples in the power network. And the rate of compute growth is expanding top-level clocking power consumption. Each of these power-related issues directly impacts BOM costs, system power budgets, and total cost of ownership in terms of power, cooling, and deployed density.
The Movellus Aeonic™ product portfolio provides an application-optimized clocking solution for AI silicon platforms that addresses lost performance due to voltage droops and enables fine-grain performance tuning for large reconfigurable architectures. Aeonic Generate can glitchlessly hop frequencies during a voltage droop to maintain reliable performance and is small enough to be distributed across the SoC for localized clocking and run-time frequency tuning. With a feature-rich, synthesizable platform, architects can use Aeonic to handle dynamic and ever-changing workloads efficiently.