Industry 1st Integrated Turnkey Solution for Droop and DVFS Response
The Aeonic Integrated Droop Response System revolutionizes the way we respond to droop in complex integrated circuits. This innovative solution is designed to simultaneously mitigate voltage droop and enable fine-grained DVFS capability in an integrated turnkey solution, resulting in significant power savings for SoCs.
It also includes extensive observability features that provides valuable insight for modern silicon health and lifecycle management systems. With its fast adaptation time, multi-threshold droop detection, remote/local droop detection support, APB & JTAG interfaces, this system helps architects manage droop and DVFS while generating actionable insights for silicon health and analytics platforms.
- IP that generates rich outbound date
- Common interfaces for silicon health and analytics management
- Programmable to adapt to silicon variation
- Tightly coupled detector and adaptive clock for fastest total (detect + respond) adaptation time
- Can reduce system power by >10%
- Supports local and remote droop detection and response
- Features that reliably port and scale from node-to-node
- Long-term R&D leverage
- Scales with process technology
Aeonic digital IP modules are silicon-proven across leading foundries, including TSMC, Intel, Global Foundries, and UMC, and are in use across multiple high-volume products.
Localized Detection and Response Use Case
Click here to learn more about how the Aeonic™ Integrated Droop Response System enables localized droop detection and response for sea of processor architectures.