Nanowatt for Edge AI | Multi-GHz for Cloud
Movellus’ silicon-proven PLL IP blocks cover a wide range of applications including audio processing, SOC processor clocking (including multi-core and AI architectures) and SERDES.
Our PLLs are currently being utilized by customers in markets spanning high-performance cloud computing to ultra low power Edge AI.
Fast turnaround time enables late-cycle PDK changes and software-enabled frequency updates to squeeze more performance from the SOC design
What is PLL IP?
PLL IP, or Phase Locked Loop, is an electronic circuit that generates an output signal whose phase is related to the phase of an input signal. A PLL IP may include a variable frequency oscillator & a phase detector in a feedback loop. Specialized technology enables traditional analog PLL IP to be implemented digitally for process portability & optimization during design.
Integer, Fractional, Spread Spectrum
Flexible architecture with integer-N, fractional-N & spread-spectrum clocking.
Input, Output & Feedback Dividers
Reference divider range: 1-512, Output divider range 1-512, Feedback divider range: 1-1024
Dynamic Bandwidth & Fast Lock
Dynamic loop filter for fast locking while maintaining excellent jitter performance in locked state. Bandwidth as high as Fref/15 and as low as 10 kHz.
PLL Status & Control
PLLs can be programmed through a parallel bus or a serial bus (e.g. AMBA). Lock status bit available.
Ultra Low Voltage Operation
Movellus PLLs do not depend on bias voltages and currents, and therefore are not headroom limited – resulting in low voltage operation of PLLs.
Ultra-Low Power PLLs
Movellus’ architecture allows us to create nano-watt customized PLLs that are orders of magnitude smaller than traditional analog PLLs.
This enables us to satisfy the most demanding requirements for even battery-less applications for markets such as Edge AI and IoT. Our very small footprint and nano-watt power consumption features are not typically available in traditional analog PLLs.
Our fast process porting allows development on non-standard process nodes in a fraction of the time of analog PLLs. Fully digital implementation relieves voltage headroom restrictions which is not possible with analog PLLs.
10 kHz to 100 MHz
700 nW to 100 uW
< 50 Tref
Applications for Movellus’ high-performance PLL IP blocks range from complex SOC clocking to high-speed SERDES, while maintaining the simplicity and ease-of-use found in all Movellus’ designs.
Maintaining key performance metrics over a wide range of input and output frequencies allows architecture tradeoff not traditionally available to SOC designers.
100 MHz to 10 GHz
< 1.2 mW/GHz
< 50 Ref. Clock Cycles