April ended with TSMC’s financial results for the 1st Quarter of 2023 reported on April 20, 2023, and their North American Technology Symposium was held on April 27 at the Santa Clara Convention Center. TSMC’s N3 entered volume production in 4Q 2022 and TSMC’s N2 “nanosheet” technology is on schedule for production in 2025.
TSMC’s CEO, C.C. Wei, said during the 1Q conference call that, “our customers’ demand for N3 exceeds our ability to supply, we expect N3 to be fully utilized in 2023, supported by both HPC and smartphone applications. Sizable N3 revenue contribution is expected to start in third quarter and N3 will contribute mid-single-digit percentage of our total wafer revenue in 2023.”
TSMC’s N3E will further extend the N3 family with enhanced performance, power and yield and is targeted for both HPC and smartphone applications. N3E is scheduled for volume production in the second half of 2023. Ramp up of N3 tape outs is expected to exceed the level N5 achieved in its first two years by roughly 2X.
Dr. Y.J. Mii, SVP, Research & Development and Technology and Dr. L.C. Lu, VP Research & Development/Design & Technology Platform, both mentioned during the North American Tech Symposium that N2 will include a novel backside power architecture to help with power delivery and routing for HPC applications that typically have dense power delivery networks. This is scheduled for 2H 2025. Along with Super High-Performance MIM (SHPMIM), which will provide 2X the capacitance density versus the previous generation, this should provide a significant advantage for building PDNs with better power integrity.
Table 1: N2 PPA comparison
Table 1 shows the expected PPA advantages of N2 vs N3E that were provided at the tech symposium.
The N7 node was referred to as a “hero” node at the symposium for the remarkable flexibility and technical advantage that it provided for TSMC. The plot in Figure 1 shows the revenue ramp for nodes from 90nm to 5nm over the past 15 years.
Figure 1: Percent wafer revenue per technology node over the last 15 years.
There are two nodes that stand out for having notable stretches of greater than 30% of the total wafer revenue, 28nm and 7nm. The gap between these nodes is filled by 20/16nm and 10nm. The “*” on the 20/16nm is just a reminder to point out that for the past few years, that revenue has practically all been due to 16nm and as one can see, 10nm was largely a “short” node to help bridge between 16nm and 7nm. 5nm has ramped well and now the 7nm and 5nm “families” of technology are over 50% of TSMC’s wafer revenue.
It will be exciting to watch TSMC launch its newer N4, N3 and N2 technologies over the next couple of years as well as their plans for continuing to build a 3D packaging ecosystem to innovate new ways to continue to scale IC designs with better PPA.
This article originally appeared on Semiconductor Engineering