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Intelligent Clock Networks

ORCHESTRATING SOC CLOCK DISTRIBUTION
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All-Digital Solution Addresses
SoC Clocking Challenges

Movellus Maestro™ clock distribution network platform delivers chip-level architectural
innovations to improve SoC performance while reducing power consumption.

Maestro solves SoC-level clock distribution challenges in high performance and ultra low power chips. This includes on-chip variation, jitter, clock skews, setup and hold violations, peak current, and switching noise. All of these clocking challenges continue to increase with process node scaling. The Maestro platform provides application-optimized digital components that intelligently orchestrate timing across an SoC.

The platform uses Movellus TrueDigital™ components which are all-digital, fully synthesizable PLLs (phase-locked loops), DLLs (delay-locked loops), Smart Clock Modules, and Virtual Mesh. These components achieve unrivaled power savings and offer superior PPA to traditional analog and partial-digital solutions. TrueDigital technology offers nanowatt power consumption, a wide voltage range, up to 10X smaller area, and low jitter.

The Maestro clocking solution with TrueDigital offers up to 30% dynamic power reduction, 15x peak power savings, 30% performance gains, and 5x faster timing signoff.

30%

Dynamic Power
Reduction

15x

Peak Power
Reduction

30%

Performance
Improvement

5x

Faster Timing
Closure

Optimizing SoC Applications

Modern applications have complex clocking requirements. Maestro provides critical clocking capabilities that are optimized for specific SoC
applications. It dramatically improve the entire chip’s power, performance, and area in a wide variety of markets.

Edge AI
Cloud
Aerospace
Industrial
IoT
Automotive
Product Line Highlights
Customizable in Weeks Fully synthesizable architecture speeds implementation
Wide Voltage & Frequency Range Enables reduced chip power consumption
Nanowatt Power Does not require precise voltage or current biasing
Up to 10X Smaller Area Not dependent on matching and passive elements
Sub-Picosecond Jitter Higher level of noise immunity than analog
Rad-Hardened Designs Radiation-hardened using existing digital libraries
Process Node Independent Supports processes from all foundries
Leverages Existing Tools Uses existing digital tools and methodologies

Movellus Products

Maestro is our flagship clock distribution network platform that intelligently orchestrates precision clocking in high performance and ultra low power SoCs. Three versions of the product are available, each addressing specific requirements based on the complexity of the application.

We also offer our all-digital fully synthesizable TrueDigital PLLs and DLLs. These two products are available for select applications that require a simple drop-in replacement for analog PLL/DLL functionality.

Maestro Cloud
Maestro AI
Maestro Phases
TrueDigital PLL
TrueDigital DLL
  • “We knew that we that had to design neural processors with not only exceptional performance, but with chips that achieve that performance at very low power and in a very small die area. Therefore, choosing the right IP partner critical for us. We put our trust in Movellus because their clock generation and CGM solutions fit our low-power architecture perfectly. They proved to be the right choice. In addition, to the architectural fit, their support from their application team helped us meet the very tight timelines we had set for introducing our solution to the market. That is the reason we continue to work with Movellus and as we work to expand our award-winning portfolio of neural decision processor for edge AI.”

    David Garrett

    Chief Architect and SVP Engineering
  • Movellus’ clocking solution had the smallest area for the frequency and process combination – no other vendor came close.

    Dr. Nathan Roberts

    VP of Engineering at Everactive Technologies
  • "With a chip that has over 1000 RISC-V processors that are running at extremely low power levels, clocking was one of the more important design considerations for this project. We work directly with the Movellus engineering team to design and debug this innovate clock distribution network. Their CGM and AWM solutions really helped us to achieve our aggressive performance targets while keeping the power within our budget."

    Darren Jones

    Vice President VLSI Engineering

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