Orchestrating Clock Distribution
in SoC Designs
The Quickest Path to the Highest Performance
The Maestro platform streamlines SoC development with an automated
and self-regulating clock distribution network.
Influencing every aspect of the system from timing closure to peak power demand, and from chip architecture to layout, the clock is probably the most complex signal in an SoC. Designs of all sizes and technology nodes experience SoC-level clock distribution challenges. On-chip variation (OCV), jitter, clock skews, peak current, switching noise, all increase with advanced process scaling.
Maestro combines clock architecture, software automation, and application-optimized IP to solve these clocking challenges. The platform includes a master RTL codebase that can be configured to generate RTL code that precisely meets application specifications. Its fully synthesizable architectures enable rapid RTL-to-GDS implementation and optimization.
TrueDigital™ PLLs, DLLs, Smart Clock Modules (SCM), Phase Shift Modules (PSM) and Virtual Mesh are configured within the platform. These all-digital modules enable unrivaled power savings and offer superior PPA to traditional analog and partial-digital solutions. Maestro is designed to work seamlessly with existing digital tools and methodologies to significantly reduce development time.
Products
Maestro Cloud
The most robust and feature-rich product for use in complex and high-performance SoC applications such as data centers and networking. A network of SCMs is connected using a VirtualMesh to regulate clocking and eliminate global clock tree skew.
Maestro AI
Streamlined for edge applications. SCMs automatically sense and compensate for OCV and skew in the clock path and equalize source latency for all blocks across the SoC. PSMs can be configured to smear circuit switching times and smooth current spikes.
Maestro Phases
This platform offers clock solutions that require TrueDigital PLL and DLL functionality, such as IoT applications. It enables design teams to reduce total power consumption for the entire chip.
TrueDigital PLL
Application-optimized PLLs can meet requirements ranging from ultra-low power nanowatt to high-performance multi-GHz. TrueDigital PLLs are silicon-proven across all foundries and are commonly used by customers in volume production.
TrueDigital DLL
TrueDigital DLLs are suitable for a variety of applications ranging from I/O lane de-skewing to clock domain alignment. Unlike other digital DLL IP blocks, these silicon-proven DLLs offer ultra-fine delay control to minimize quantization noise.
