Join us at Booth 2417 to learn more about our Aeonic™ Digital IP platform which solves system-level challenges in areas including power and performance optimization and monitoring in a manner that is configurable, synthesizable and process portable! If you are a chip/system architect, physical design lead, or just interested in new system-level IP solutions, come by to learn how the Aeonic Digital IP platform maximizes performance in a completive power envelope!

Movellus will also be hosting a panel at the DAC Pavilion on Tuesday, July 11th, 2:00pm – 2:45pm PDT. This panel investigates design considerations and tradeoffs for 2.5D chiplet solutions, and features industry innovators and leaders from Deca Technologies, Marvell, Movellus, and Siemens EDA. Ed Sperling from Semiconductor Engineering will be moderating this panel.

To learn more about the panel, click here

To register for DAC, click here

To schedule some time in our VIP suite or on the main floor, click here