Patent Notice

Aeonic Generate™ Patents

Patent NumberPatent TitleCountry of Issue
US9641183B2DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONSUnited States
US9515668B2AUTOMATICALLY PLACE-AND-ROUTED ADPLL WITH PWM-BASED DCO RESOLUTION ENHANCEMENTUnited States
US10158365B2DIGITAL, RECONFIGURABLE FREQUENCY AND DELAY GENERATOR WITH PHASE MEASUREMENTUnited States
US10587275B2LOCKED LOOP CIRCUIT WITH CONFIGURABLE SECOND ERROR INPUTUnited States
US9698798B1DIGITAL CONTROLLER FOR A PHASE-LOCKED LOOPUnited States
US9680480B1FRACTIONAL AND RECONFIGURABLE DIGITAL PHASE-LOCKED LOOPUnited States
US9705516B1RECONFIGURABLE PHASE-LOCKED LOOP WITH OPTIONAL LC OSCILLATOR CAPABILITYUnited States
US9762249B1RECONFIGURABLE PHASE-LOCKED LOOPUnited States
US10594323B2LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATIONUnited States
US10594323B2LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATIONUnited States
US11070215B2LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATIONUnited States
US11070216B2LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATIONUnited States
US11239849B2LOCKED LOOP CIRCUIT AND METHOD WITH MULTI PHASE SYNCHRONIZATIONUnited States
US11831318B1FREQUENCY MULTIPLIER SYSTEM WITH MULTI-TRANSITION CONTROLLERUnited States
US11493950B2FREQUENCY COUNTER CIRCUIT FOR DETECTING TIMING VIOLATIONSUnited States

Aeonic Connect™ Patents

Patent NumberPatent TitleCountry of Issue
US10713409B2INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUCTIONUnited States
US10972106B1PHASE AND DELAY COMPENSATION CIRCUIT AND METHODUnited States
US11165432B1GLITCH-FREE DIGITAL CONTROLLED DELAY LINE APPARATUS AND METHODUnited States
US11374578B2ZERO-OFFSET PHASE DETECTOR APPARATUS AND METHODUnited States
US20220200604A1DIGITAL SYSTEM SYNCHRONIZATIONUnited States

Company-Wide Patents

Patent NumberPatent TitleCountry of Issue
US10614182B2TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITSUnited States
US10031992B2CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC SYNTHESIS AND INTEGRATIONUnited States
US10740526B2INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUCTIONUnited States
US11017138B2TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITSUnited States
US10972119B1REGULATED CHARGE SHARING ANALOG-TO-DIGITAL CONVERTER (ADC) APPARATUS AND METHODUnited States
US11128308B2REGULATED CHARGE SHARING APPARATUS AND METHODSUnited States
US10972115B1METHODS AND APPARATUS FOR CALIBRATING A REGULATED CHARGE SHARING ANALOG-TO-DIGITAL CONVERTERUnited States
US11496139B2FREQUENCY MEASUREMENT CIRCUIT WITH ADAPTIVE ACCURACYUnited States