Optimizing Vmin Search with On-Die “Oscilloscopes”

Researchers undervolted a production Armv8 server processor and cut its average energy use by 19.4% with no performance loss^[1]. Where did that energy come from? It came from the voltage guardband, the margin that keeps the operating voltage from dipping below Vmin.

Vmin is the lowest voltage a system-on-chip (SoC) can run at each frequency. Every P-state, adaptive voltage scaling (AVS) target, and dynamic voltage and frequency scaling (DVFS) setpoint rests on that number. Teams establish it on the bench and the tester: automatic test pattern generation (ATPG), functional patterns, and system-level test (SLT) step the supply down at each frequency until the part fails. Engineers then stack guardband over that result to cover what the tester never exercised: real workloads, temperature, aging, and droop.

Why the Guardband Grows

The stack grows because no external probe watches the failure point. A bench scope has the bandwidth but sits too far from the transistor to catch the transients that matter. First-order droops live on-die, where local capacitance and package inductance filter the nanosecond content before it reaches a ball or board sense point. Figure 1 shows one event at two points on the power delivery network (PDN).

The scope reports a smoothed, spatially averaged trace while the voltage at each transistor swings further and varies across the floorplan. The difference between that trace and the worst droop on the die becomes guardband. On high-performance processors, the band can top 15% of nominal supply^{[2] [3]}.

Vmin search is hard for two reasons: design teams must craft the worst-case droop, and they must align that droop with the timing failures it induces. Get either wrong and the Vmin is wrong too.

Building a Worst-Case Droop

Vmin search is conceptually simple. Post-silicon teams sweep a frequency for a specific workload, cycle-align the droop it generates with the exercised critical path, and repeat across DVFS points, blocks, and corners.

Building the worst case is harder, bordering on art. ATPG generates high-speed transients but often unrealistic patterns, with no control over the droop during cycle activation. Functional tests target realistic paths but rarely produce the deepest droop, because no team can write every vector and workload. Different workloads stress the PDN differently, and some align resonant droops across the package and board into new worst cases.

Teams cover the uncertainty two ways: added margin and system-level testing. Padded margins blow up power budgets quadratically (the V² relationship). SLT runs the shipped stack on a near-real platform and catches a margin that is too thin, but it cannot prove a margin is too bloated.

A worst-case droop is necessary but not sufficient: its trough must also cycle-align with the exercised critical path, and that rarely happens on its own. The lowest-voltage test may not exercise the worst timing path, and the workload that does may droop early or late. When no one can read the voltage at the failing path, the only way to extract Vmin is to force the worst droop and the worst path into the same cycle and watch for the failure. Doing that for every critical path and every droop would take a year of experienced post-silicon engineers.

Picking a Sensor

Now suppose the voltage were observable at the paths that fail. The two worst cases would no longer need to meet in one test. One run could activate the limiting paths and record the voltage at which each fails; another could drive the PDN to its deepest droop and record how low the rail actually swings. That is the job of a Vmin sensor: voltage, at the right locations, at nanosecond speed.

On-die DC voltage sensors. Many SoCs already carry voltage sensors inside a process, voltage, and temperature (PVT) monitor, which report the steady-state level of a supply domain at a few points. Each reading averages the rail over microseconds or longer, so the nanosecond droops that set Vmin vanish before the sensor reports them.

Path margin monitors (PMMs). A PMM reports how close a tapped path is to failing, not the voltage at the transistor. Vmin is defined in volts, and a PMM never reports one. Turning a margin into a voltage floor means correlating it against failing voltage, path by path and part by part, and the tapped paths come from pre-silicon static timing analysis (STA), an educated guess until silicon confirms it.

Placement widens the gap. The most critical paths sit in the most congested routing, where physical designers reject any added resistance or capacitance that would force another place-and-route respin. PMMs land on the paths that could be tapped, not necessarily the paths that limit Vmin.

Package and board probe points. Probe points stand in for on-die behavior, but they sit on the wrong side of the package and report at microsecond rates, too slow for on-die transients. They also work only on the bench, where equipment, lab space, and effort per device cap the part count.

Aeonic Insight™ PDNIQ 2. PDNIQ 2 measures near-transistor voltage across the die at nanosecond resolution, fast enough to capture the transients that set Vmin. Designers can compare the waveforms that functional and ATPG content produce and pick out the worst case for each critical path. Table 1 scores each sensor against what the search needs.

A full Vmin strategy still uses DC sensors for the static rail level, margin monitors for specific paths, and board sensors for the regulator. Vmin search, though, asks one question: what is the lowest voltage the logic survives under its worst droop?

Vmin Search with PDNIQ 2

The distributed sensors sit at the likely worst-droop locations, in and around high-current-density regions such as vector units, multiply-accumulate (MAC) arrays, and network-on-chip (NoC) routers. Running its sensors in parallel, PDNIQ 2 records the minimum and maximum voltage each location saw during a test. When a failure occurs, single-sensor mode returns the time-stamped waveform of the transient, as Figure 2 shows.

The search then splits into two runs that never have to meet. When a path fails on the tester or in the system, the test team reads the near-transistor voltage at that cycle and location: the voltage at which that path fails. In a separate run, product engineers execute the content that stresses the PDN hardest and record the deepest trough at each location. Because both results are in volts, the team sets the regulator floor so the deepest trough stays above every measured failure voltage, plus the margin they choose.

That flow repeats across workloads without a year of hand alignment, from bench characterization through production test, and it follows the silicon into the field. A new model or day-zero workload can induce a droop worse than any the bench conceived. Teams can run the same Vmin search on deployed parts to characterize the new workload and prevent or root-cause in-field failures.

Conclusion

Vmin search comes down to two hard problems: crafting the worst-case droop and aligning it with the paths that fail. The common sensors leave teams guessing at the second. DC sensors average away the nanosecond droop, PMMs see only the paths they tap, and probe points sit on the wrong side of the package. That guesswork ships as guardband.

PDNIQ 2 replaces the guess with a measurement: near-transistor voltage across the die at nanosecond resolution. With failures and droops both recorded in volts, teams capture them in separate tests and set the regulator floor from the two results, on the bench, in production test, and in the field. The guardband held for guesswork comes back as lower power or more performance headroom.

Schedule a Technical Deep Dive

A technical deep dive starts with your silicon. A Movellus engineer walks through your PDN and your Vmin flow: how your test content builds worst-case droop, how it aligns that droop with timing failures, and where PDNIQ 2 would read near-transistor voltage, on the bench and in the field. To schedule a session, contact sales@movellus.com. For the power-management principles behind this flow, read the Movellus whitepaper Foundations of Power Management in the Age of AI ^[4].

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References

1. G. Papadimitriou et al., Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins, IEEE Transactions on Device and Materials Reliability, 2020.

2. C. R. Lefurgy et al., Active Management of Timing Guardband to Save Energy in POWER7, 44th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2011.

3. V. J. Reddi et al., Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling, 43rd IEEE/ACM International Symposium on Microarchitecture (MICRO), 2010.

4. A. Jani, Foundations of Power Management in the Age of AI: Axioms to Maximize Compute Density, Movellus Circuits, Inc., white paper, rev. 1.00, Sep. 2026. movellus.com/foundations-of-power-management-in-the-age-of-ai