Movellus LDOs – Coming in 2020
Movellus’ all-digital LDOs offer critical flexibility for large SoCs with a variety of voltage domains.
Our proprietary LDO architecture is clocked and eliminates the need for bandgap voltage references.
Movellus LDOs are architected to be robust against environmental and process variations while occupying the least amount of silicon area.
Integer, Fractional, Spread Spectrum
Flexible architecture with integer-N, fractional-N & spread-spectrum clocking.
Input, Output & Feedback Dividers
Reference divider range: 1-512, Output divider range 1-512, Feedback divider range: 1-1024
Dynamic Bandwidth & Fast Lock
Dynamic loop filter for fast locking while maintaining excellent jitter performance in locked state. Bandwidth as high as Fref/15 and as low as 10 kHz.
PLL Status & Control
PLLs can be programmed through a parallel bus or a serial bus (e.g. AMBA). Lock status bit available.
Ultra Low Voltage Operation
Movellus PLLs do not depend on bias voltages and currents, and therefore are not headroom limited – resulting in low voltage operation of PLLs.