Movellus DLLs

DDRs | Clock Domain Crossing | IO Deskewing

Movellus DLLs are suitable for a variety of applications, ranging from I/O lane de-skewing to clock domain alignment to to DDRs.

Unlike other digital DLL IP blocks, Movellus’ silicon-proven DLLs offer ultra fine delay control to minimize quantization noise.

Like all Movellus products, our DLLs consume a minimum number of routing layers, employ standard DFT features, and allow easy migration to new processes or PDKs.

What is DLL IP?

DLL IP, or delay locked loop, is an electronic circuit similar to a phase-locked loop, but with a tunable delay line instead of an internal oscillator. DLL is used to advance or delay clock or data signals in a variety of applications.

Low Voltage Operation

Movellus DLLs can work under low voltage supplies, and do not require specialized analog voltages.

Quick Customization

Movellus DLLs can be customized in a matter of days to meet different frequency/delay specifications.

Configuration & Control

Our DLLs can be programmed through a parallel bus or a serial bus (e.g. AMBA). Lock status bit available.

Process Portable

Movellus DLLs are portable across any process node which eliminates significant redesign, and integration overhead.

Wide Frequency Range

Movellus DLLs can cover a wide range of frequencies from 100 MHz all the way up to 4GHz.

Clock-Domain Alignment

Movellus’ domain-alignment DLLs simultaneously provide significant reduction in clock uncertainty and alignment between two independent clock trees with different insertion delays.

Aligning clocks at interfaces allows CDC-free communication between flops between hierarchical blocks. Lower clock uncertainty results in significant reductions in power and timing closure dominated by hold violations, or a reduction in setup time to enable faster clock rates and SOC throughput.

Frequency Range

100 MHz to 2 GHz

Delay Range

300 ps to 1800 ps

Step Size

< 10 ps

Lock Time

< 50 Tclk


Applications such as chip-to-chip IO links or parallel hard disk read/write heads require alignment of multiple bits with varying arrival times.

Movellus’ master/slave DLL architecture uses a master lane to calibrate the core DLL characteristics thus minimizing circuitry required in the slave DLLs.

Frequency Range

300 MHz to 1.33 GHz

Delay Range

1.2 UI

Step Size

< 5 ps

Lock Time

< 50 Tclk