Dynamic workloads can cause localized voltage droops that create transient or potentially catastrophic mission mode failures. Aeonic Generate AWM detects and responds to droops swiftly, resulting in more reliable performance for customer workloads.

Localized Droop 

Response - Use Case

Domain-Specific Droop Response - Use Case

Generate AWM Data Sheet

Click Here to register and learn more about the Aeonic Generate AWM platform to swiftly and reliably resolve droop 

Click Here (no registration required) to learn more about how to combat localized droop response for customer driven driven workloads.

Click Here (no registration required) to learn more about how Aeonic Generate AWM helps architects respond to domain-specific droop.

Up to 8x smaller than multi-output, fractional, analog PLLs, and half as small as comparable integer generators

Programmable through a common register interface for run-time frequency control

Glitchless frequency transitions for in-time, reliable droop response

System architects can respond to droops with adaptive clocking, which scales frequency down and up during voltage fluctuation. The technique requires a programmable clock and sometimes a droop detector. The latter can be optional if architects have deterministic workloads that can be managed with prior knowledge, which is rare for merchant silicon providers. The figure on the left shows how Movellus Aeonic Generate products can respond to a droop after VDD crosses the pre-set threshold. Design teams can reclaim Vmin margin reducing system power while maintaining or increasing system performance through adaptive clocking.

An architect would pair an Aeonic Generate AWM module with a droop detector for the processor cluster and associated voltage domain to rapidly respond to workload-driven localized droops. This allows designers to deliver localized and independent droop response without altering the performance of neighboring processor clusters.

While application-specific accelerators significantly improve performance and power efficiency, they can face localized droops from dynamic workloads or induce droops under heavy load.

The figure on the right shows an example architecture of an ADAS processor with the Aeonic Generate AWM Platform for localized droop support. An architect would pair an AWM module with an application-specific sub-block or accelerator to respond to workload-driven localized droops within five clock cycles with glitchless and rapid frequency shifts.

"With a chip that has over 1000 RISC-V processors that are running at extremely low power levels, clocking was one of the more important design considerations for this project. We work directly with the Movellus engineering team to design and debug this innovate clock distribution network."

"MosChip has successfully designed a hard macro of Movellus’ AWM soft IP macro implemented for a mutual customer’s 7nm automotive-grade AI computing platform ASIC, meeting an aggressive tape-out schedule...Movellus has been phenomenal with their partner support."

"We believe Movellus’ silicon IP will facilitate upgrading and innovating silicon platforms while delivering significant size, weight and power (SWaP) advantages in a wide range of mission-critical military and commercial applications."

Darren Jones

Vice President VLSI Engineering

Swamy Irrinki

SVP World Wide Sales

Chris Rappa

Director of FAST Labs

To find out specifically how Movellus Aeonic Generate™ AWMs can reliably respond to droop with glitchless frequency shifts contact us today.

After you submit this form, a member of our team will contact you with specific information about how Aeonic Generate enables system-level solutions for large SoCs.

Copyright © 2023 Movellus Circuits Inc, all rights reserved • Terms of Service • Privacy Policy